ARCHITECTURE OF DATA PLANE DEVELOPMENT KIT (DPDK) FOR ACCELERATING PACKET PROCESSING AND TRAFFIC PROTECTION AT 100 GBPS AND BEYOND

Abstract

This article presents a comprehensive analysis of the Data Plane Development Kit (DPDK) architecture as a framework for achieving high-performance packet processing at rates of 100 Gbps and above. The work examines the key architectural components of DPDK, including the Environment Abstraction Layer (EAL), Poll Mode Drivers (PMD), memory management subsystem (rte_mbuf, rte_mempool, rte_ring), and packet processing models (run-to-completion, pipeline, event-driven, and graph framework). Special attention is given to the mechanisms enabling kernel-bypass, zero-copy data paths, and cache-optimized processing that collectively allow DPDK-based applications to approach wire-speed performance on modern multi-core processors. The article also addresses the integration of cryptographic traffic protection mechanisms (IPsec, MACsec) through the rte_security and cryptodev subsystems, analyzing the trade-offs between inline and look-aside processing approaches. The prospects for FPGA-based network accelerators that combine high-speed switching and hardware-level traffic encryption within the DPDK ecosystem are discussed. The findings provide a technical reference for network engineers and researchers developing high-performance, security-aware data plane solutions for next-generation telecommunications and data center infrastructures.